1. Technical Field
The invention relates generally to a redundancy system for semiconductor devices, and more particularly to a redundancy architecture that enhances yield while decreasing access delays.
2. Background Art
Since the early 1970's, redundancy has been used to substitute spare rows/columns of memory cells for faulty rows/columns of cells in a memory array. In such systems, the memory is tested after manufacture and before encapsulation to detect faulty rows/columns. The addresses of these faulty lines are set in polysilicon fuses, using laser and/or electrical fuse blow techniques. Each redundant address decoder has its own dedicated set of fuses. The redundant decoders receive incoming row/column address signals, and compare these signals to the addresses stored in the fuses. If a match occurs, the redundant row/column associated with the particular redundant decoder is accessed, and the memory row/column is disabled such that data is read from and/or written to the redundant row/column.
In addition to fuses, other non-volatile storage means have been used to store the address of a faulty row/column. U.S. Pat. No. 3,755,791, entitled "Memory System With Temporary Or Permanent Substitution Of Cells For Defective Cells," issued to Arzubi and assigned to IBM, teaches the use of a latch made up of non-volatile devices such as MNOS transistors. An article by Fitzgerald et al, "Semiconductor Memory Redundancy At The Module Level," IBM Technical Disclosure Bulletin, Vol. 23, No. 8, January 1981 pp. 3601-02 teaches the use of FAMOS devices. In both references, non-volatile storage is emphasized because such cells can be programmed after the memory is packaged and sold to the customer. In other words, because the redundancy data can be updated after chip encapsulation, redundancy can be programmed at the module level to correct bits that fail in the field.
Another alternative that has developed is the use of fuses that provide inputs to latches. Under the control of clock signals, the fuses are interrogated, and the data therefrom is used to set the state of static latches. The latched data can now be updated in the field, without losing the original redundancy data stored in the fuses. Examples of such arrangements include U.S. Pat. No. 4,532,607, entitled "Programmable Circuit Including A Latch To Store A Fuse's State," issued to Uchida and assigned to Toshiba; U.S. Pat. No. 4,614,881, entitled "Integrated Semiconductor Circuit Device For Generating A Switching Control Signal Using A Flip-Flop Circuit Including CMOS FET's And Flip-Flop Setting Means," issued to Yoshida et al. and assigned to Fujitsu; and the article "Volatile Redundancy Fuse Selection And Read Back," IBM Technical Disclosure Bulletin, Vol. 32, No. 6B, November 1989 pp. 450-51. See also an article by Singh et al, "Fault-Tolerant Memory Chip Architecture For Yield Enhancement And Field Repair," IBM Technical Disclosure Bulletin, Vol. 26, No. 1, June 1983 pp. 342-43, wherein the redundant address is stored in a shift register dedicated to fix field fails.
In general, the number of row/column lines in memory chips doubles with each generation. While there have been some attempts in the art to reduce the number of redundant rows/columns while retaining the same potential fault coverage (e.g. by sharing redundant elements between adjacent arrays--see the article "Efficient Use Of Redundant Bit Lines For Yield Optimization," IBM Technical Disclosure Bulletin, Vol. 31, No. 12, May 1989 pp. 107-08), the industry practice has been to increase the number of redundant bits in direct proportion to the increase in the number of data bits stored by the memory. The increased density/complexity of the overall redundancy system provides an increased likelihood of faults.
For example, since each redundant address decoder has its own dedicated set of fuses, this means that the number of fuses doubles each generation. As the number of fuses increases, so does the extent to which fuse operations detract from overall yield. For example, if laser-blown fuses are used, as the number of fuses increases the likelihood that a given fuse will be partially blown (by virtue of misalignment between the laser spot and the fuse to be blown) also increases, thus setting an incorrect address in the redundant address decoder and permitting access to a faulty line of cells. Since faulty memory cells already sharply limit yield, the overall process yield is extremely intolerant to non-cell yield detractors such as faulty fuse blow.